Technical Field
The present invention generally relates to forming a vertical transport fin field effect transistor (VT FinFET) having reduced leakage current due to gate-induced-drain leakage (GIDL) and increased carrier injection, and more specifically to implementing a higher band gap on the drain side of a VT FinFET and a high germanium concentration silicon-germanium source on the opposite side of the vertical fin from the high bandgap drain.
Description of the Related Art
A Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and FinFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. The channel for the FinFET can be an upright slab of thin approximately rectangular Si, commonly referred to as the fin with a gate on the fin, as compared to a metal-oxide-semiconductor field effect transistor (MOSFET) with a gate parallel with the plane of the substrate.
Depending on the doping of the source and drain, an n-type FET (NFET) or a p-type FET (PFET) can be formed. An NFET and a PFET can be coupled to form a complementary metal oxide semiconductor (CMOS) device, where a p-channel MOSFET and n-channel MOSFET are coupled together.
A current can flow even when the gate is in an electrical state that places a FET in an “off” state due to several leakage mechanisms. Carriers can move across a p-n junction around the drain region causing a leakage current. Gate-induced-drain leakage (GIDL) can occur at the drain side of a FET due to the electrical potential generated by the gate. GIDL can be caused by multiple mechanisms, including but not limited to, band-to-band tunneling (BTBT) and trap assisted tunneling.
With ever decreasing device dimensions, forming the individual components and electrical contacts become more difficult. An approach is therefore needed that retains the positive aspects of traditional FET structures, while overcoming the scaling issues created by forming smaller device components, including channel lengths and gate dielectric thicknesses.